PDB=0, SPI0=0, DMAMUX=0, USBDCD=0, SPI1=0, PIT=0, CRC=0, FTM0=0, I2S=0, FTFL=0
System Clock Gating Control Register 6
FTFL | Flash Memory Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
DMAMUX | DMA Mux Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
RNGA | RNGA Clock Gate Control |
SPI0 | SPI0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
SPI1 | SPI1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
I2S | I2S Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
CRC | CRC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
USBDCD | USB DCD Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PDB | PDB Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PIT | PIT Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
FTM0 | FTM0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
FTM1 | FTM1 Clock Gate Control |
FTM2 | FTM2 Clock Gate Control |
ADC0 | ADC0 Clock Gate Control |
RTC | RTC Access Control |